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We have been committed to conduct high-quality research activities related with VLSI/SoC design and CAD software since February 1989.

VLSI/SoC DESIGN AREA

  • Plasma Display Panel (PDP)
    • High-performance PDP controller
    • ASIPs (Application Specific Instruction Set Processor) for high-performance PDPs
    • Picture quality improvement (algorithm and hardware implementation)
  • Liquid Crystal Display (LCD)
    • Picture quality improvement : algorithm and hardware implementation
    • Image compression for frame buffer size reduction
  • Cryptographic Hardware: power-attack insusceptible circuit techniques
  • Multimedia applications

CAD AREA

  • SoC design methodology
    • Timing modeling and verification of IPs
    • Transaction-level design methodology
  • Low-power circuit design techniques: MTCMOS and multi-VDD circuit design techniques
  • Analysis of circuit effects by UDSM/nano-scale process
    • Power network noise analysis
    • Gate-level delay modeling under crosstalk

Laboratory where passion really matters!

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CAD and SoC Design Lab. Division of Electrical and Computer Engineering,
POSTECH, San 31 Hyoja-Dong, Pohang 790-784, Republic of KOREA.
Voice : +82-54-279-2878, 2893 FAX : +82-54-279-5933
E-mail : youngk@postech.ac.kr